1. Field of the Invention
This invention relates to semiconductor devices, semiconductor wafers, chip size packages (CSP), and wafer level chip size packages (WLCSP). This invention also relates to manufacturing methods and inspection methods for semiconductor wafers.
This application claims priority on Japanese Patent Applications Nos. 2004-327784 and 2005-52988, the contents of which are incorporated herein by reference.
2. Description of the Related Art
Recently, electronic devices such as notebook personal computers and portable telephones having digital cameras have been rapidly developed so as to reduce dimensions, thickness, and weights thereof, whereby conventionally-known dual inline packages have been replaced with chip size packages encapsulating semiconductor devices.
Various types of semiconductor devices encapsulated in chip size packages have been developed and put into practical use; and Japanese Unexamined Patent Application Publication No. H09-252027 discloses an example of a semiconductor device encapsulated in a chip size package. Herein, an integrated circuit is formed on the surface of a semiconductor substrate and is covered with a resin sealing layer.
Semiconductor devices of chip size packages are produced in such a way that a semiconductor wafer having a plurality of integrated circuits, which are formed on the surface in a lattice-like manner and are each encompassed by scribing regions, are subjected to dicing (or cutting) using a dicing blade along scribing lines, thus separating individual semiconductor chips.
FIG. 9 is a cross-sectional view showing the structure of a conventionally-known semiconductor wafer in proximity to a dicing line (or a cut region) after dicing, wherein reference numeral 1 designates a silicon substrate; reference numeral 2 designates a field oxide film that is formed on a main surface 1 a of the silicon substrate 1; reference numerals 3a to 3c designate first, second, and third interlayer insulating films that are formed separately formed on the field oxide film 2; reference numerals 4a to 4c designate seal rings that are separately formed above an opening 2a of the field oxide film 2; reference numeral 5 designates a passivation film that covers the third interlayer insulating film 3c and the sealing ring 4c; reference numeral 6 designates a scribing line (or a scribing region); reference numeral 7 designates a chip region (i.e., a region for use in the formation of components of a semiconductor device); and reference numeral 8 designates a dicing line (or a cut region).
In a dicing step, a width w of the dicing line 8 and a width W of the scribing line 6 are respectively set in such a way that a positional shift s, by which a center axis Ax′ of the dicing line 8 shifts from a center axis Ax of the scribing line 6, converges into a regular range. For example, when the width w of the dicing line 8 is set to 50 μm, the width W of the scribing line 6 is set to approximately 100 μm.
FIG. 10 is a plan view showing the layout of the conventionally-know semiconductor wafer after the dicing step, wherein reference numerals 11 designate individual semiconductor chips that are separated by the dicing lines 8; and reference numerals 12 designate solder balls that are formed in a matrix manner in each of the semiconductor chips 11, wherein the solder balls 12 are electrically connected to integrated circuits (not shown) that are formed on the main surface 1a of the silicon substrate 1.
There is a possibility of the occurrence of degradation of ones of the semiconductor chips 11 in which the dicing lines 8 exceed prescribed allowance due to positional shifts in dicing and partially extend into the chip regions 7, thus causing damage to the seal rings 4a to 4c. Such damage of the seal rings 4a to 4c makes it easy for the water content in the air to infiltrate into internal regions of the semiconductor chips 11. This becomes a factor in degrading the reliability in manufacturing over time; hence, it is necessary for the manufacturer to perform inspections.
There are provided two inspection methods as follows:
(1) First Inspection Method
In FIG. 10, distances t1 and t2 between each solder ball 12 and rectangular ends 13 and 14 of each semiconductor chip 11; then, a distance d between the seal ring 4c and the dicing line 8 is calculated based on the distances t1 and t2.
(2) Second Inspection Method
With respect to each product lot, a prescribed number of semiconductor chips 11 are extracted and are then subjected to damaging at peripheral portions thereof, thus directly measuring the distance d between the seal ring 4c and the dicing line 8.
In each of the aforementioned inspection methods, it is judged that damage may be unlikely to occur when the distance d belongs to a regular range, so that the corresponding product lot is judged to be a good product. In contrast, when the distance d exceeds the regular range, it is judged that damage may likely occur, so that the corresponding product lot is judged to be a defective product.
As for the first inspection method, the distances t1 and t2 between the solder balls 12 and the rectangular ends 13 and 14 of the semiconductor chip 11 are relatively long and are measured based on the positioning of the solder balls 12 that are arranged with a relatively low precision of patterning; hence, the measurement precision for the distances t1 and t2 becomes low. For this reason, there is a drawback in that the precision for the calculation of the distance d between the seal ring 4c and the dicing line 8 becomes low because of the low measurement precision for the distances t1 and t2. In addition, the first inspection method requires a specially-designed device for measuring the distances t1 and t2, which is troublesome.
The second inspection method directly measures the distance d between the seal ring 4c and the dicing line 8; hence, the measurement precision for the distance d becomes high; however, it takes a long time and requires troublesome work to perform the inspection. In addition, the second inspection method is a so-called destructive inspection; hence, after the inspection, the semiconductor chips become useless.
In order to avoid the occurrence of curvature and crack in semiconductor substrates during dicing, it may be necessary for silicon wafers to have structures including the following technical features.    (1) Channels are formed in conformity with boundaries between integrated circuits on the backside of a silicon substrate by use of a dicing blade; thereafter, the surface of the silicon substrate is sealed with a resin and is then subjected to cutting along the channels by use of the dicing blade, thus producing individual chip size packages, an example of which is disclosed in Japanese Unexamined Patent Application Publication No. 2000-124168.    (2) Channels having rectangular shapes in cross sections or V-shaped channels are formed in scribing regions on the surface of a silicon substrate; then, the overall surface of the silicon substrate including the channels is sealed with a resin, thus completing a silicon wafer. The surface of the silicon substrate is subjected to cutting along the rectangular channels or the V-shaped channels by use of a dicing blade having a reduced thickness, thus producing chip size packages, examples of which are disclosed in Japanese Unexamined Patent application Publication No. 2000-195862 and Japanese Unexamined Patent Application Publication No. H11-111896.    (3) Channels having relatively large widths are formed in scribing regions on the surface of a silicon substrate; then, the surface of the silicon substrate including the channels is sealed with a resin, thus completing a silicon wafer. Thereafter, the backside of the silicon substrate is subjected to polishing (or grinding) so that the broad channels are exposed on the backside of the silicon substrate; then, the surface of the silicon substrate is subjected to cutting along the channels, thus producing chip size packages, an example of which is disclosed in Japanese Unexamined Patent Application Publication No. 2001-85363.
FIG. 18 is a cross-sectional view showing a silicon wafer having the aforementioned structure (1), wherein reference numeral 101 designates a silicon substrate; reference numeral 102 designates a scribing region on a main surface 101a of the silicon substrate 101; reference numerals 103 designate integrated circuit forming regions defined by the scribing region 102; reference numerals 104 designate integrated circuits that are formed in the integrated circuit forming regions 103 respectively; reference numeral 105 designates a resin sealing layer for entirely covering the main surface 101a including the integrated circuits 104; and reference numeral 106 designates a boundary channel that is formed at a prescribed position on a backside 101b of the silicon substrate 101 in conformity with the scribing region 102.
The boundary channel 106 is formed using a dicing blade whose thickness is approximately set to 100 μm.
When a chip size package is produced using the aforementioned silicon wafer, the surface of the resin sealing layer 105 and the surface 101a of the silicon substrate 101 is subjected to cutting along the boundary channel 106 by use of the aforementioned dicing blade.
When a chip size package is produced using the silicon wafer having the aforementioned structure (1), the surface 101a of the silicon substrate 101 are subjected to cutting by use of the dicing blade whose thickness substantially matches the width of the scribing region 102. As shown in FIG. 19, a dicing channel 112, which is formed by cutting the surface 101a by use of a dicing blade 111, may deviate from the boundary channel 106 on the backside 101b with a positional shift d therebetween. After completion of dicing, this may cause chipping (or shell-like cracks) 113, cracks 114, and burrs 115 in a certain portion interconnecting the dicing channel 112 and the boundary channel 106 in the silicon substrate 101.
Problems due to the occurrence of the chipping 113, cracks 114, and burrs 115 may occur in the other silicon wafers having the aforementioned structures (2) and (3) as well; hence, it seems that they are common in all wafers for use in manufacturing of chip size packages.